As semiconductor devices continue to shrink in size, the contact resistance tends to increase and become more significant. Accordingly, there is a need to reduce the specific contact resistivity to keep the contact resistance within usable bounds. Specific resistivities below about 7×10−9 Ω·cm2 are desirable, but difficult to achieve using common metal-on-semiconductor or metal-nitride-on-semiconductor approaches.
For some semiconductors such as p-type Ge, Fermi-level pinning near the valence band provides sufficiently low contact resistivity. For n-type devices including those comprising Si, Ge, SiGe, or InGaAs semiconductors, other methods are required. For example, Agrawal et al. (“A unified model for insulator selection to form ultra-low resistivity metal-insulator-semiconductor contacts to n-Si, n-Ge, and n-InGaAs,” Appl. Phys. Let., 101, 042108 (2012)) disclose metal-insulator-semiconductor (MIS) contacts having a thin interfacial dielectric inserted between the metal and the semiconductor. The dielectric layer is thin enough that electrons can tunnel through the layer. These structures have the effect of unpinning the Fermi level and lowering the barrier height. Contact structures were formed and modeled using Al conductors and interfacial layers comprising various oxides and other chalcogenides including TiO2, Al2O3, La2O3, ZnS, ZnSe, SrTiO3, ZnO, Ta2O5, GeO2, CdO, and SnO2. Specific contact resistivities to n-Si as low as 10−9 Ωcm2 were obtained, which were described as five times lower than that of the “state-of-the-art” NiSi/n-Si structure at the same doping. These data are illustrated in FIG. 1.